Electron Backscatter Diffraction (EBSD)
Equal Channel Angular Extrusion
70% Cold Rolled
Copper layers in a roll-bonded Cu-Nb Metal Composite before and after annealing.
Courtesy of Samuel Lim and Prof. A.D. Rollett, Carnegie Mellon University
Interconnect lines formed by the Damascene process.
Example: J.-Y. Cho, K. Mirpuri, D. N. Lee, J.-K. An and J. A. Szpunar (2005). "Texture investigation of copper interconnects with a different line width." Journal of Electronic Materials 34: 53-61.
A copper film sample analyzed using Transmission-EBSD (t-EBSD)
Forward Scatter Detector (FSD) image collected from a copper film sample prepared by FIB liftout, showing strong crystallographic contrast within the thinned center region
A combined image quality and inverse pole figure orientation map from within the thinned region
An FSD image at higher magnification from the center area of the thinned region
A corresponding image quality and inverse pole figure orientation map from approximately the same region collected with a 5 nm step size
Transmission-EBSD (t-EBSD) scan of Copper
Image quality (left) and inverse pole figure (right) of a t-EBSD scan of Cu using a 2.5 nm step size
Three-dimensional integrated circuits (3-D IC) have emerged as a promising route for high performance systems to meet the growing demands of mobile computing. Through-silicon vias (TSV) connect multiple device levels into a single integrated circuit. This approach eliminates edge wiring requirements, reduces the electrical path-length, provides faster device operation, and reduces power consumption. The reliability of copper TSVs depends on both deposition conditions and the thermal loading used during the 3-D IC manufacturing process. Optimization of both the deposition and thermal annealing conditions is important for maximizing device lifetime.
Orientation map of copper TSV showing no preferred orientation
Grain maps of copper TSV with twin boundaries included and excluded from grain
Kernel average misorientation map showing the plastic strain developing after thermal cycling, which can reduce reliability
ChI-Scan™ analysis of a polished printed circuit board. The grain maps below are from the copper phase (left) and the kovar phase (right), where grains are randomly colored to show size and morphology. The copper phase has a bimodal grain size distribution with larger grains adjacent to the kovar interface and smaller grains away from it. This suggests two different deposition and grain growth mechanisms were active during the deposition process. The kovar phase has a more homogeneous grain distribution. The grain size distributions from both phases are shown below (right). Analysis of the grain misorientations indicates that the kovar phase has significant twinning (approximately 50% of the grain boundaries within the phase) while the copper phase has far fewer twin boundaries (approximately 7%). This type of detailed analysis would not be possible without the accurate phase differentiation provided by ChI-Scan™.
EBSD grain maps for copper phase (left) and kovar phase (right) showing a bimodal grain structure for the copper phase
Grain size distribution for copper and kovar phases
Copper damascene test structures which have been analyzed using OIM. The maps show the identified copper grains as raw data (left), the result of applying the standard OIM twin-finding algorithm with removal of all twins (center), and the result of applying the twin coherency test with only the coherent twins being removed (right).
Selected individual scans are shown from an in-situ heating experiment on a copper specimen deformed through equal channel angular extrusion
Energy Dispersive Spectroscopy (EDS)
ChI-Scan™ analysis of printed circuit board metals
EDS elemental map for copper
EDS elemental map for iron
ChI-Scan™ phase map for printed circuit board metals
Micro X-ray Fluorescence (Micro-XRF)
Bronze spectra with electron (red) and X-ray (black) excitation